1. Field of the Invention
The present invention relates to clock switching circuits and, in particular, to a glitchless clock switching circuit. This circuit allows all inputs, including both clock inputs and the clock select input, to be completely asynchronous to each other.
2. Discussion of the Prior Art
While glitchless clock switching circuits are well known in the prior art, each of these circuits suffers from at least one of the following disadvantages: use of asynchronous delays such as digital one shots, long clock switching latency, sensitivity to large clock buffer skew, incompatibility with scan based chip test and complex, non-minimal hardware implementation. The clock switching circuit of the present invention does not suffer from any of these disadvantages.
The glitchless clock switching circuit described below can be employed in a wide variety of applications. These applications include switching high/low speed clocks in microprocessors, switching reference clocks in phase locked loops and switching reference clocks in frequency synthesizers.